Department of Computer Science and Engineering
FACULTY OF CSE DEPARTMENT      
 

Prof.(Dr.) Kirti Gupta
HOD CSE
Bharati Vidyapeeth's College of Engineering 

 

E-mail: kirti.gupta@bharatividyapeeth.edu

Office Phone: (011) 25258637, 25278443 Extn.: 240

Qualification:

Ph. D (Electronics and Communication), Delhi Technological University

M. Tech (Information Technology), University School of Information Technology, Guru Gobind Singh Indraprastha University, New Delhi

B. Tech (Electronics and Communication Engineering), Indira Gandhi Institute of Technology, New Delhi

Area of Specialisation:

VLSI Design, Digital Circuits

Work Experience:

Teaching: 16 years

Seminar/Conference/FDP/Workshop Attended: 05

Other Activities: Senior Member IEEE

       Life member ISTE

Subjects Taught: Analog Electronics, VLSI Design, Digital System Design

Papers Published: 80

Scores: Impact Factor: 14

              RG Score: 14. 87

              H-Index: 6

              I-10 Index: 3

List of Publications:

  1. Shourya Gupta, Kirti Gupta, Neeta Pandey, “Pentavariate Vmin Analysis of A Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write And Divided Bit-Line Read,” IEEE Transactions on Circuits and Systems -I: Regular Papers. (Accepted)

  2. Gupta, Kirti Gupta, Neeta Pandey, “A 32nm Subthreshold 7T SRAM bit cell with Read Assist,” IEEE Transactions on VLSI systems, vol. 25, n0 12, pp.3473-3483, 2017.

  3. Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, and Jeebananda Panda, “On Improving the Performance of Dynamic DCVSL Circuits,” Journal of Electrical and Computer Engineering, Article ID 8207104, vol. 2017, 11 pages, 2017.

  4. Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal, “New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies,” Journal of Circuits, Systems and Computers, (SCI Expanded), 1750186, 15 pages, 2017.

  5. Kirti Gupta, Neeta Pandey, “Analysis and Design of MOS Current Mode Logic Circuits with Passive Inductor Load,” International Journal of Advance Research in Science and Engineering, vol. 6, no.11, pp:498-506, 2017.

  6. Kirti Gupta, “Performance Evaluation of Different Read Ports in Static Random Access Memory in 45 nm CMOS Technology,” International Journal of Advance Research in Science and Engineering, vol. 6, no.11, pp. 1461-1466, 2017.

  7. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Dynamic Positive-Feedback Source-Coupled Logic (D-PFSCL)” in Taylor and Francis, International Journal of Electronics, vol. 103, no.10, pp. 1626-1638, 2016.

  8. Neeta Pandey, Kirti Gupta, Bharat Choudhary, “New Proposal for MCML based Three-Input Logic Implementation,” VLSI Design, Article ID 8712768, vol. 2016, 10 pages, 2016. IF: 0.404

  9. Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal, “Bus Implementation Using New Low Power PFSCL Tristate Buffers,” Active and Passive Electronic Component, Article ID 4517292, vol. 2016, 8 pages, 2016.

  10. Neeta Pandey, Damini Garg, Kirti Gupta, and Bharat Choudhary, “Hybrid Dynamic MCML style (H-DyCML): A High Speed Dynamic MCML style,” Journal of Engineering, Article ID 8027150, vol. 2016, 8 pages, 2016.

  11. Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary, “MOS Current Mode Logic Exclusive-OR Gate using Multi-threshold Triple-tail Cells,” Elsevier, Microelectronics Journal, vol. 57, pp. 13-20, 2016.

  12. Nitish, Neeta Pandey, Kirti Gupta, Manu Kumar Saini, “DFAL based flexible multi-modulo prescaler,” ICTACT Journal on Microelectronics,  vol. 2, no. 3, pp. 273-280, 2014.

  13.  Neeta Pandey, Kirti Gupta, Maneesha Gupta, “An Efficient Triple-tail Cell based PFSCL D-latch,” Elsevier, Microelectronics Journal, vol. 45, no. 8, pp. 1001-1007, 2014.

  14. Neeta Pandey, Kirti Gupta, Rajeshwari Pandey, Rishi Pandey, Tanvi Mittal, “Novel Oscillators in Subthreshold Regime;” International Journal of Electrical and Electronics Engineers vol. 6,no.2,pp.151-156, 2014.

  15. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Analysis and Design of MOS Current Mode Logic Exclusive-OR Gate using Triple-tail Cells” Elsevier, Microelectronics Journal, vol. 44, no. 6, pp. 561-567, 2013.

  16. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low-power Tri-state Buffer in MOS Current Mode Logic,” in Springer, Analog Integrated Circuits and Signal Processing, vol. 75, no. 1, pp. 157-160, 2013.

  17. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low-Voltage MOS Current Mode Logic Multiplexer,” Radio Engineering (SCI Expanded), vol. 22, no. 1, 259-268, 2013.

  18. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “MCML D-Latch Using Triple-Tail Cells: Analysis and Design,” Active and Passive Electronic Component, Article ID. 217674, vol. 2013, 9 pages, 2013.

  19. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “MOS Current Mode Logic with Capacitive Coupling,” ISRN Electronics, Article ID 473257, vol. 2012, 7 pages, 2012.

  20. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Multi-Threshold MOS Current Mode Logic based Asynchronous Pipeline Circuits,” ISRN Electronics, Article ID 529194, vol. 2012, 7 pages, 2012.

  21. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MCML Array Multiplier,” vol. 6 no. 2, 2012.

  22. Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “New Low Power Tri-state Circuits in Positive Feedback Source Coupled Logic” in Journal of Electrical and Computer Engineering, Article ID 670508, vol. 2011, 6 pages, 2011.

  23. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A New Active Shunt-peaked MCML based High Performance 1:8 Demultiplexer for Serial Communication,” International Journal of Engineering and Technology, vol. 2, no. 10, pp: 4632-4639, 2010.

 

List of Publications in Conference

  1. Rahul Kumar Agrawal, Neeta Pandey, Kirti Gupta,  “Implementation of PFSCL Razor Flip flop,” In the proceedings of IEEE 2017 International Conference on “Computing Methodologies and Communication”, ICCMC, pp. 6-11.

  2. Utkarsh Mittal, Kirti Gupta, “On the Implementation of PFSCL Configurable Logic Block with High-Impedance State,” In the proceedings of International Conference on “Recent Innovations in Science, Agriculture, Engineering and Management” pp. 1157-1162.

  3. Kirti Gupta, Neeta Pandey, Naman Saxena, Shruti Dutta, “Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies,” In the proceedings of International Conference on Computational Science and Its Applications – ICCSA 2017, pp. 299-313.

  4. Sourabh Singh, Kirti Gupta, “Data Encryption on FPGA using Huffman Coding,” In the proceedings of International Conference on “Recent Innovations in Science, Agriculture, Engineering and Management, pp: 1163-1168.

  5. Kirti Gupta. Neeta Pandey, “Analysis and Design of MOS Current Mode Logic Circuits with Active Inductor Load,” In the proceedings of 10th International Conference on Science, Technology and Management , pp. 291-300.

  6. Kirti Gupta, “Adiabatic logic for Ultra low power application,” 4th International Conference on Recent Advances in Engineering Science and Management   (ICRAESM-17), pp. 255-262.

  7. Akash Singh Rawat, Kirti Gupta, “Efficient 500 MHz Digital Phase Locked Loop Implementations in 180nm CMOS Technology,” In the proceedings of 10th International Conference on Science, Technology and Management , 311-320.

  8. Kartik Jain, Kirti Gupta, “An Ultra-low Voltage Hybrid OTA Based Low Pass Filter,” In the proceedings of 10th International Conference on Science, Technology and Management, pp. 306-310.

  9. Neeta Pandey, Kirti Gupta, Stuti Gupta, Suman Kumari, “MCML based Priority Encoders,” 4th International Conference on Recent Advances in Engineering Science and Management   (ICRAESM-17), 246-254.

  10. Shourya Gupta, Kirti Gupta and Neeta Pandey, “Stability Analysis of Different Dual-Port SRAM cells in Deep Submicron Region using N-Curve Method,” in proceedings of IEEE ICSC-2016, pp. 431-436.

  11. Kirti Gupta, Prayanshu Sharma and Neeta Pandey, “Design of low power subthreshold linear feedback shift register,” in proceedings of 1st IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems 2016, pp. 1-6.

  12. Kirti Gupta, Shrey Bagga and Neeta Pandey, “Efficient CVSL full adder realizations,” in proceedings of 1st IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems 2016, pp. 1-5.

  13. Shourya Gupta, Kirti Gupta, Neeta Pandey, “Performance Evaluation of SRAM cells for Deep Submicron Technologies,” Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, pp. 292-296, 2016.

  14.  Kirti Gupta, Pragati Shukla, Neeta Pandey, “ On the Implementation of PFSCL Adders,” Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, pp. 287-291, 2016. 

  15.  Gurashish, Ankit, Kirti Gupta, Neeta Pandey, “FPGA Implementation of different NRZ Line Coding Schemes,” IEEE India Inter National Conference on Information Processing, pp. 1-7, 2016.

  16. Neeta Pandey, Naman Saxena, Kirti Gupta, “Implementation of Asynchronous Pipeline using Transmission Gate logic”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 101-106, 2016.

  17. Neeta Pandey, Abhishek, Kirti Gupta, “PFSCL based Linear Feedback Shift Register”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 580-585, 2016.

  18. Neeta Pandey, Nitish, Kirti Gupta, “Pre-scalar for Diode Free Adiabatic Logic Family”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 481-485, 2016.

  19. Kirti Gupta, Utkarsh Mittal, Rahul Baghla, Pragati Shukla, Neeta Pandey, “On the Implementation of PFSCL Serializer,” in proceedings of in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 436-440, 2016.

  20. Kirti Gupta, Utkarsh Mittal, Rahul Baghla, Neeta Pandey, “Implementation of PFSCL based Demultiplexer,” in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 490-494, 2016.

  21. Samiksha Agarwal, Neeta Pandey, Kirti Gupta, Bharat Choudhary, “Design of MCML based LFSR for Low Power and Mixed Signal Applications,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-6, 2015.

  22. Nitish, Neeta Pandey, Kirti Gupta, Rajeshwari Pandey, “DFAL based Implementation of Frequency Divider-by-3,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-6, 2015.

  23. Neeta Pandey, Maneesha Gupta, Kirti Gupta, “A PFSCL based Configurable Logic Block,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-4, 2015.

  24. Radhika, Neeta Pandey, Kirti Gupta, Maneesha Gupta, “Low Power D-latch Design using MCML Tri-state Buffers” in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 531 – 534, 2014.

  25. Neeta Pandey, Rashmi Pandey, Trisha Mittal, Kirti Gupta, “Ring and Coupled Ring oscillators in Subthreshold region,” in proceedings of International Conference on Signal Propagation and Computer technology, pp. 132-136, 2014.

  26. Himanshu Puri, Kshitij Ghai, Kirti Gupta, Neeta Pandey, “A Novel DFAL based Frequency Divider” in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 526 – 530, 2014.

  27. Himani Jawa, Kirti Gupta, “Novel Compressors in the Sub-threshold Regime”, in proceedings of IEEE International Conference on Signal Processing and Communication (ICSC), pp. 424 – 427, 2013. 

  28. Kirti Gupta, Radhika Tanwar, Neeta Pandey, Maneesha Gupta, “A Novel High Speed MCML Square Root Carry Select Adder for Mixed-Signal Applications” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 194-197, 2013.

  29. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Performance Improvement of PFSCL Gates through Capacitive Coupling” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp.185-188, 2013.

  30. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low Power Multi-Threshold MOS Current Mode Logic Asynchronous Pipeline Circuits” in proceedings of IEEE 5th India International Conference on Power Electronics (IICPE), pp. 1-4, 2012.

  31. Kirti Gupta, Ranjana Sridhar, Neeta Pandey, Maneesha Gupta, “A New Improved Current Mode Logic Style with Feedback for Wireless Communication” in proceedings of Annual IEEE India Conference (INDICON), pp.1-4, 2011.

  32. Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “A New Current Mode Logic Style with Feedback for Digital Applications” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 164-167, 2011.

  33. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MOS Current Mode Logic C-Element for Asynchronous Pipelines” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 122-125, 2011.

  34. Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “Performance Comparison of MCML and PFSCL Gates in 0.18μm CMOS Technology” in proceedings of IEEE International Conference on Computer and Communication Technology, pp. 230-233, 2011.

  35. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Shunt-Peaking in MCML Memory Element Design in 0.18μm CMOS Technology” in proceedings of Annual IEEE India Conference (INDICON), pp. 1-4, 2010.

  36. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MCML-based High Speed Four-Bit Ripple-Carry Adder” in proceedings of IEEE International Conference on Computer and Communication Technology, pp. 285-289, 2010.

 Papers presented/participated in conference

  1. Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low power VLSI circuits for mobile wireless computing systems,” National Conference on Mobile Computing (MOBILE COMP-2008).

  2. Rahul Bahl, Kirti Gupta, “Insurance Information Warehouse,” National Conference on Future Trends in Information Technology (FIT- 2005).

  3. M.K. Raina, Kirti Gupta, Yogita Arora, “Electromagnetic Interference Compatibility for Mobile Communication System, URSI, General Assembly, Time and Frequency section, National Physical Laboratory, 2005.

 

 

Seminar/Conference/FDP/Workshop Attended: 05

Other Activities: A member of IEEE, ISTE